Date of Award:
Doctor of Philosophy (PhD)
Electrical and Computer Engineering
Aravind R. Dasu
A tool flow is presented for deriving simulated annealing accelerator circuits on a field programmable gate array (FPGA) from C source code by exploring architecture solutions that conform to a preset template through scheduling and mapping algorithms. A case study carried out on simulated annealing-based Autonomous Mission Planning and Scheduling (AMPS) software used for autonomous spacecraft systems is explained. The goal of the research is an automated method for the derivation of a hardware design that maximizes performance while minimizing the FPGA footprint. Results obtained are compared with a peer C to register transfer level (RTL) logic tool, a state-of-the-art space-borne embedded processor and a commodity desktop processor for a variety of problems. The automatically derived hardware circuits consistently outperform other methods by one or more orders of magnitude.
Phillips, Jonathan D., "A C to Register Transfer Level Algorithm Using Structured Circuit Templates: A Case Study with Simulated Annealing" (2008). All Graduate Theses and Dissertations. Paper 215.
Copyright for this work is retained by the student.