Date of Award:

Spring 2014

Document Type:

Thesis

Degree Name:

Master of Science (MS)

Department:

Electrical and Computer Engineering

Advisor/Chair:

Tam Chantem

Abstract

Recent studies have shown that significant power savings are possible with the use of in- exact processors, which may contain a small percentage of errors in computation. However, use of such processors in time-sensitive systems is challenging as these processors significantly hamper the system performance. In this thesis, a design framework is developed for real-time applications running on stochastic processors. To identify hardware error pat- terns, two methods are proposed to predict the occurrence of hardware errors. In addition, an algorithm is designed that uses knowledge of the hardware error patterns to judiciously schedule real-time jobs in order to maximize real-time performance. Both analytical and simulation results show that the proposed approach provides significant performance improvements when compared to an existing real-time scheduling algorithm and is efficient enough for online use.