Date of Award:
Master of Science (MS)
Electrical and Computer Engineering
The design of a common architecture that can support multiple data-flow patterns (or contexts) embedded in complex control flow structures, in applications like multimedia processing, is particularly challenging when the target platform is a Field Programmable Gate Array (FPGA) with a heterogeneous mixture of device primitives. This thesis presents scheduling and mapping algorithms that use a novel area cost metric to generate resource aware context adaptable architectures. Results of a rigorous analysis of the methodology on multiple test cases are presented. Results are compared against published techniques and show an area savings and execution time savings of 46% each.
Samala, Harikrishna, "Methodology to Derive Resource Aware Context Adaptable Architectures for Field Programmable Gate Arrays" (2009). All Graduate Theses and Dissertations. Paper 484.
Copyright for this work is retained by the student.