Date of Award:

5-2010

Document Type:

Dissertation

Degree Name:

Doctor of Philosophy (PhD)

Department:

Electrical and Computer Engineering

Committee Chair(s)

Brandon Eames

Committee

Brandon Eames

Committee

Aravind Dasu

Committee

Koushik Chakraborty

Committee

Sanghamitra Roy

Committee

Scott Budge

Committee

Steve Allan

Abstract

Scheduling, placement, and routing are important steps in Very Large Scale Integration (VLSI) design. Researchers have developed numerous techniques to solve placement and routing problems. As the complexity of Application Specific Integrated Circuits (ASICs) increased over the past decades, so did the demand for improved place and route techniques. The primary objective of these place and route approaches has typically been wirelength minimization due to its impact on signal delay and design performance. With the advent of Field Programmable Gate Arrays (FPGAs), the same place and route techniques were applied to FPGA-based design. However, traditional place and route techniques may not work for Coarse-Grained Reconfigurable Architectures (CGRAs), which are reconfigurable devices offering wider path widths than FPGAs and more flexibility than ASICs, due to the differences in architecture and routing network. Further, the routing network of several types of CGRAs, including the Field Programmable Object Array (FPOA), has deterministic timing as compared to the routing fabric of most ASICs and FPGAs reported in the literature. This necessitates a fresh look at alternative approaches to place and route designs. This dissertation presents a finite domain constraint-based, delay-aware placement and routing methodology targeting an FPOA. The proposed methodology takes advantage of the deterministic routing network of CGRAs to perform a delay aware placement.

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47d45f076af705deda2352c521bf6998

Comments

This work made publicly available electronically on August 2, 2010.

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