Date of Award:
Master of Science (MS)
Electrical and Computer Engineering
Stochastic iterative decoding is a novel method to decode the bits received at the end of a communication channel and to control the rate of error happening in the message bits due to noise being injected into the channel. This decoder uses stochastic computation that is based on manipulation of probabilities from a random sequence of digital bits. Hardware needed for implementing this arithmetic is very simple and can be completely implemented using simple digital complementary metal oxide gates. This helps the decoder to be technology independent, which is a major advantage over its digital and analog counterparts, which are complex and technology dependent. But this decoder presents a new set of problems when nodes in stochastic decoders can get locked to a fixed state if the stochastic streams are correlated due to the presence of cycles in a decoder's factor graph. To overcome this problem, additional logic has to be introduced on every edge of the decoder to break this correlation. This work presents application-specific-integrated-circuit (ASIC) design and simulation of the digital core of a stochastic iterative decoder in 0.18um technology (Spec- tre). This thesis also examines gate complexity and power onsumption of the decoder with edge-memory, tracking forecast memory, and dual-counter hysteresis techniques in place.
Payak, Keyur M., "Complexity and Power Consumption in Stochastic Iterative Decoders" (2010). All Graduate Theses and Dissertations. Paper 808.
Copyright for this work is retained by the student.