Date of Award:
Master of Science (MS)
Electrical and Computer Engineering
The integral image representation of an image is important for a large number of modern image processing algorithms. Integral image representations can reduce computation and increase the operating speed of certain algorithms, improving real-time performance. Due to increasing demand for real-time image processing performance, an integral image architecture capable of accelerating the calculation based on the amount of available resources is presented. Use of the proposed accelerator allows for subsequent stages of a design to have data sooner and execute in parallel. It is shown here how, with some additional resources used in the Field Programmable Gate Array (FPGA), a speed increase is obtained by using a one-dimensional Systolic Array (SA) approach. Additionally, extra guidelines are given for further research in this area.
De la Cruz, Juan Alberto, "Field-Programmable Gate Array Implementation of a Scalable Integral Image Architecture Based on Systolic Arrays" (2011). All Graduate Theses and Dissertations. Paper 854.
Copyright for this work is retained by the student.