Date of Award
Master of Science (MS)
Electrical and Computer Engineering
Supporting a variety of communication protocols has typically required extensive hard- ware and Input/Output (I/O) interfaces targeting each protocol specifically. Recent designs in the past ten years have created more dynamic approaches by using Field Programmable Gate Arrays (FPGAs) and embedded hardware to implement or simulate previous hardware I/O designs. With the constant increase in FPGA and embedded technologies the capabilities of dynamic implementations have expanded. This report addresses the design of an up-to-date reconfigurable multi-faceted embedded device targeting recent technological advances in FPGAs.
Dunkley, Richard, "Development of a Reconfigurable Multi-Faceted Communications Device Using Partial Dynamic Reconfiguration" (2011). All Graduate Plan B and other Reports. Paper 9.
Copyright for this work is retained by the student.