Session

Technical Session VII: 12th Annual Frank J. Redd Student Competition

SSC04-VII-2.pdf (244 kB)
Presentation Slides

Abstract

Elevated levels of radiation in Low Earth Orbit (LEO) can cause several unexpected behaviors in digital logic. These behaviors, known as Single Event Effects (SEEs), manifest themselves in two ways: unexpected short circuits (Single Event Latch Ups), and erroneous bit flips (Single Event Upsets). Protecting memory from SEEs is usually done via some type of SECDEC controller, and protecting IO can be done in a number of ways -- the simplest of which entails using upper level protocols to verify data integrity. Several techniques are currently employed to deal with SEEs in microprocessors including radiation hardening, radiation shielding, software redundancy, and hardware redundancy. TREMOR uses a hardware solution based on an architecture known as Triple Modular Redundancy to achieve SEE tolerance. This paper discusses the TREMOR FPGA system and how it will be used to synchronize the processors and ensure that no erroneous data propagates to the system bus. It will also discuss how the flexibility of this design will allow TREMOR to become a new test bed for various implementations of the TMR architecture.

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Aug 11th, 11:15 AM

TREMOR: A Triple Modular Redundant Flight Computer and Fault-Tolerance Testbed for the WPI Pansat Nanosatellite

Elevated levels of radiation in Low Earth Orbit (LEO) can cause several unexpected behaviors in digital logic. These behaviors, known as Single Event Effects (SEEs), manifest themselves in two ways: unexpected short circuits (Single Event Latch Ups), and erroneous bit flips (Single Event Upsets). Protecting memory from SEEs is usually done via some type of SECDEC controller, and protecting IO can be done in a number of ways -- the simplest of which entails using upper level protocols to verify data integrity. Several techniques are currently employed to deal with SEEs in microprocessors including radiation hardening, radiation shielding, software redundancy, and hardware redundancy. TREMOR uses a hardware solution based on an architecture known as Triple Modular Redundancy to achieve SEE tolerance. This paper discusses the TREMOR FPGA system and how it will be used to synchronize the processors and ensure that no erroneous data propagates to the system bus. It will also discuss how the flexibility of this design will allow TREMOR to become a new test bed for various implementations of the TMR architecture.