Proceedings - Design Automation Conference
Institute of Electrical and Electronics Engineers
National Science Foundation
The AI boom is bringing a plethora of domain-specific architectures for Neural Network computations. Google's Tensor Processing Unit (TPU), a Deep Neural Network (DNN) accelerator, has replaced the CPUs/GPUs in its data centers, claiming more than 15 × rate of inference. However, the unprecedented growth in DNN workloads with the widespread use of AI services projects an increasing energy consumption of TPU based data centers. In this work, we parametrize the extreme hardware underutilization in TPU systolic array and propose UPTPU: an intelligent, dataflow adaptive power-gating paradigm to provide a staggering 3.5 ×-6.5× energy efficiency to TPU for different input batch sizes.
Pramesh Pandey, Noel Gundi, Sanghamitra Roy and Koushik Chakraborty, UPTPU: Improving Energy Efficiency of a Tensor Processing Unit through Underutilization Based Power-Gating. Proceedings of the IEEE/ACM Design Automation Conference (DAC), December 2021, San Francisco, California (Accepted).