BoostNoC: Power Efficient Network-on-Chip Architecture for Near Threshold Computing
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
I E E E Computer Society
National Science Foundation
While near threshold design space provides a promising approach towards energy-efficient computing, it is plagued by sub-optimal performance. Application characteristics and hardware non-idealities of conventional architectures (optimized for the nominal voltage) prevent us from fully leveraging the potential of NTC systems. Further, the popular approach of increasing the computational core count to compensate for the performance loss severely burdens the on-chip communication fabric with an increased communication demand. In this work, we quantitatively analyze the performance bottleneck createdby a conventional NoC architecture in many-core NTC systems. To reclaim the performance lost due to a sub-optimal NoC, we propose BoostNoC - a power efficient, multi-layered network-on-chip architecture. BoostNoC improves the system performance by nearly 2x over a conventional NTC system. Further, we improve the energy efficiency by 1.4x with the use of drowsy routers.
Chidhambaranathan R, Rajesh JayashankaraShridevi, Sanghamitra Roy and Koushik Chakraborty, BoostNoC: Power Efficient Network-on-Chip Architecture for Near Threshold Computing. IEEE/ACM International Conference on Computer-aided Design (ICCAD), Article 24, pp. -8, November 2016.