DAC '12: Proceedings of the 49th Annual Design Automation Conference
Association for Computing Machinery
In this paper, we present a novel technique for early prediction of timing violations in high-performance pipelined microprocessors. We show that a static instruction in a microprocessor, identified by its Program Counter (PC), is an excellent predictor of an upcoming timing violation. Our analysis combines architectural data collected from real program execution with gate level logic analysis. Exploiting this PC based timing violation predictability, we propose a robust system design that predicts and tolerates timing violations seamlessly in a pipelined microprocessor. Under two different faulty environments, we show 20.9-89.8% and 14.6-80.6% average performance improvements in real programs over other state-of-the-art techniques, respectively. © 2012 ACM.
Sanghamitra Roy and Koushik Chakraborty, Predicting Timing Violations Through Instruction Level Path Sensitization Analysis. IEEE/ACM Design Automation Conference (DAC), pp. 074-08, June 2012, San Francisco, CA.
© 2012. This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in DAC '12: Proceedings of the 49th Annual Design Automation Conference, http://dx.doi.org/10.1145/10.1145/2228360.2228555.