Power-Performance Yield Optimization for MPSoCs Using MILP
Thirteenth International Symposium on Quality Electronic Design (ISQED)
Institute of Electrical and Electronics Engineers
In nanometer technology regime, process variation (PV) causes uncertainties in the processor frequency and leakage power, affecting the overall performance and energy efficiency of Multi-Processor System-on-Chips (MPSoCs). Mostly, the Power and Performance Yield optimizations are not done simultaneously while scheduling the tasks at the system level. We demonstrate the significance of optimizing both Power and Performance Yields simultaneously in task scheduling in order to minimize the effects of process variation at the system level. In this paper, we present process variation aware task scheduling algorithms and define a new design metric, called Power-Performance Yield (PPY) to guide the scheduling procedure. The PPY is modeled considering the spatial correlation characteristic of systematic process variation, log-normal distributions of leakage power and an energy-aware slack budgeting approach. We propose a novel mathematical formulation using Mixed Integer Linear Programming (MILP) technique and also employ an improved Simulated Annealing (SA) based stochastic technique for PPY optimization. The experimental results on TGFF generated random task graphs and E3S benchmark suite demonstrate average PPY improvements of 16.9% and 31% over two other SA based schemes that separately optimize Performance Yield and Power Yield, respectively. With accurate PV-aware modeling, we obtain average PPY improvements of 9.65% and 30.3% under strong correlations and 12.9% and 29.8% under weak correlations when compared to two other existing scheduling schemes that lack appropriate modeling. © 2012 IEEE.
Kshitij Bhardwaj, Sanghamitra Roy and Koushik Chakraborty, Power-Performance Yield Optimization for MPSoCs Using MILP, IEEE International Symposium on Quality Electronic Design (ISQED), pp. 764-77, March 202, San Jose, CA.