ACM Transactions on Design Automation of Electronic Systems
Association for Computing Machinery
In this article, we demonstrate that the sensitized path delays in various microprocessor pipe stages exhibit intriguing temporal and spatial variations during the execution of real-world applications. To effectively exploit these delay variations, we propose dynamically adaptable resilient pipeline (DARP)-a series of runtime techniques to boost power-performance efficiency and fault tolerance in a pipelined microprocessor. DARP employs early error prediction to avoid amajor portion of the timing errors.We combine DARP with the state-of-art topologically homogeneous and power-performance heterogeneous (THPH) architecture to build up a new frontier for the energy efficiency of multicore processors (DARP-MP). Using a rigorous circuitarchitectural infrastructure, we demonstrate that DARP substantially improves the multicore processor performance (9.4-20%) and energy efficiency (10-28.6%) compared to state-of-the-art techniques. The energyefficiency improvements of DARP-MP are 42% and 49.9% compared against the original THPH and another state-of-art multicore power management scheme, respectively.
Hu Chen, Sanghamitra Roy and Koushik Chakraborty, DARP-MP: Dynamically Adaptable Resilient Pipeline Design in Multicore Processors, ACM Transactions on Design Automation of Electronic Systems (TODAES), Article No: 3, Vol. 2, Issue, November 2015.