Analysis of Intermittent Timing Fault Vulnerability

Authors

Saurabh Kothawade, Utah State University
Koushik Chakraborty, Utah State UniversityFollow
Sanghamitra Roy, Utah State UniversityFollow
Yiding Han, Utah State University

Document Type

Article

Journal/Book Title/Conference

Microelectronics Reliability

Volume

52

Issue

7

Publisher

Elsevier Ltd

Publication Date

7-1-2012

Funder

National Science Foundation

First Page

1515

Last Page

1522

Abstract

Continuous scaling of transistor feature size rapidly increases the effect of intermittent faults. These faults manifest as timing violations due to the combined effects of process variation, circuit wear-out, and variation in environmental conditions. In this paper, we combine all critical sources of intermittent faults in a comprehensive framework. Our experiments with the MIPS-789 processor reveal that at the 22nm technology node, the combined effect of all the factors can degrade the delay by 2.5X. Such gross delay degradation extending more than two cycles can render many recently proposed time borrowing techniques ineffective. We analyze three architectural techniques to mitigate intermittent faults and evaluate them using full system architectural simulation. © 2012 Elsevier Ltd. All rights reserved.

Recommended Citation

Saurabh Kothawade, Koushik Chakraborty, Sanghamitra Roy, and Yiding Han, Analysis of Intermittent Timing Fault Vulnerability, Elsevier Journal of Microelectronics Reliability (MR), pp. 55-522, Vol. 52, Issue 7, July, 2012.