Document Type

Article

Journal/Book Title/Conference

IEEE Journal on Selected Topics in Quantum Electronics

Volume

2

Issue

1

Publisher

IEEE

Publication Date

1996

First Page

97

Last Page

105

DOI

10.1109/2944.541878

Abstract

This paper describes the VLSI design, layout, and testing of a Hybrid-SEED smart pixel array for a four-stage intelligent optical backplane. The Hybrid-SEED technology uses CMOS silicon circuitry with GaAs-AlGaAs multiple-quantum-well modulators and detectors. The chip has been designed based on the HyperPlane architecture and is composed of four smart pixels which act as a logical 4-bit parallel optical channel. It has the ability to recognize a 4-bit address header, inject electrical data onto the backplane, retransmit optical data, and extract optical data from the backplane. In addition, the smart pixel array can accommodate for optical inversions and bit permutations by appropriate selections of multiplexers. Initial data pertaining to the electrical performance of the chip will be provided and a complete logical description will be given.

Comments

Originally published by IEEE. Publisher's PDF can be accessed through the IEEE Journal of Selected Topics in Quantum Electronics.

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