IEEE Journal on Selected Topics in Quantum Electronics
This paper describes the VLSI design, layout, and testing of a Hybrid-SEED smart pixel array for a four-stage intelligent optical backplane. The Hybrid-SEED technology uses CMOS silicon circuitry with GaAs-AlGaAs multiple-quantum-well modulators and detectors. The chip has been designed based on the HyperPlane architecture and is composed of four smart pixels which act as a logical 4-bit parallel optical channel. It has the ability to recognize a 4-bit address header, inject electrical data onto the backplane, retransmit optical data, and extract optical data from the backplane. In addition, the smart pixel array can accommodate for optical inversions and bit permutations by appropriate selections of multiplexers. Initial data pertaining to the electrical performance of the chip will be provided and a complete logical description will be given.
D.R. Rolston, D.V. Plant, T.H. Szymanski, H.S. Hinton, W.S. Hsiao, M.H. Ayliffe, D. Kabal, M.B. Venditti, A.V. Krishnamoorthy, K.W. Goossen, J.A. Walker, B. Tseng, S.P. Hui, J.C. Cunningham, and W.Y. Jan, "A Hybrid-SEED Smart Pixel Array for a Four-Stage Intelligent Optical Backplane Demonstrator," IEEE Journal on Selected Topics in Quantum Electronics. Vol. 2, No.1, April 1996, pp. 97-105.