Date of Award:
5-2012
Document Type:
Thesis
Degree Name:
Master of Science (MS)
Department:
Electrical and Computer Engineering
Committee Chair(s)
Koushik Chakraborty
Committee
Koushik Chakraborty
Committee
Sanghamitra Roy
Committee
Edmund Spencer
Abstract
Degradation of transistor parameter values due to Negative Bias Temperature Instability (NBTI) has emerged as a major reliability problem in current and future technology generations. NBTI Aging of a Static Random Access Memory (SRAM) cell leads to a lower noise margin, thereby increasing the failure rate. The register file, which consists of an array of SRAM cells, can suffer from data loss, leading to a system failure. In this work, we study the source of NBTI stress in an architecture and physical register file. Based on our study, we modified the register file structure to reduce the NBTI degradation and improve the overall system reliability. Having evaluated new register file structures, we find that our techniques substantially improve reliability of the register files. The new register files have small overhead, while in some cases they provide saving in area and power.
Checksum
9576e30acf3b016cd8f4adbdd57926b5
Recommended Citation
Kothawade, Saurahb, "Design of Negative Bias Temperature Instability (NBTI) Tolerant Register File" (2012). All Graduate Theses and Dissertations. 1160.
https://digitalcommons.usu.edu/etd/1160
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Comments
This work made publicly available electronically on April 10, 2012.