Date of Award:
12-2008
Document Type:
Dissertation
Degree Name:
Doctor of Philosophy (PhD)
Department:
Electrical and Computer Engineering
Committee Chair(s)
Aravind R. Dasu
Committee
Aravind R. Dasu
Committee
Brandon Eames
Committee
Nicholas Flann
Committee
Stephen Allan
Committee
Charles Swenson
Abstract
A tool flow is presented for deriving simulated annealing accelerator circuits on a field programmable gate array (FPGA) from C source code by exploring architecture solutions that conform to a preset template through scheduling and mapping algorithms. A case study carried out on simulated annealing-based Autonomous Mission Planning and Scheduling (AMPS) software used for autonomous spacecraft systems is explained. The goal of the research is an automated method for the derivation of a hardware design that maximizes performance while minimizing the FPGA footprint. Results obtained are compared with a peer C to register transfer level (RTL) logic tool, a state-of-the-art space-borne embedded processor and a commodity desktop processor for a variety of problems. The automatically derived hardware circuits consistently outperform other methods by one or more orders of magnitude.
Checksum
e1d62fd21a2bd9abaaa6de224237e921
Recommended Citation
Phillips, Jonathan D., "A C to Register Transfer Level Algorithm Using Structured Circuit Templates: A Case Study with Simulated Annealing" (2008). All Graduate Theses and Dissertations, Spring 1920 to Summer 2023. 215.
https://digitalcommons.usu.edu/etd/215
Copyright for this work is retained by the student. If you have any questions regarding the inclusion of this work in the Digital Commons, please email us at .