Date of Award:

5-2016

Document Type:

Thesis

Degree Name:

Master of Science (MS)

Department:

Electrical and Computer Engineering

Department name when degree awarded

Computer Engineering

Committee Chair(s)

Thidapat Chantem

Committee

Thidapat Chantem

Committee

Koushik Chakraborty

Committee

Ryan Gerdes

Abstract

The shift from uniprocessor to multi-core architectures has made it difficult to design predictable hard real-time systems (HRTS) since guaranteeing deadlines while achieving high processor utilization remains a major challenge. In addition, due to increasing demands, energy efficiency has become an important design metric in HRTS. To obtain energy savings, most multi-core systems use dynamic voltage and frequency scaling (DVFS) to reduce dynamic power consumption when the system is underloaded. However, in many multi-core systems, DVFS is implemented using voltage and frequency islands (VFI), implying that individual cores cannot independently select their voltage and frequency (v/f) pairs, thus resulting in less energy savings when existing energy-aware task assignment and scheduling techniques are used. In this thesis, we present an analysis of the increase in energy consumption in the presence of VFI. Further, we propose a semi-partitioned approach called EDF-hv to reduce the energy consumption of HRTS on multi-core systems with VFI. Simulation results revealed that when workload imbalance among the cores is sufficiently high, EDF-hv can reduce system energy consumption by 15.9% on average.

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1264bbc3209201019752fbd07139b2d8

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