Date of Award:
5-2016
Document Type:
Dissertation
Degree Name:
Doctor of Philosophy (PhD)
Department:
Electrical and Computer Engineering
Advisor/Chair:
Sanghamitra Roy
Abstract
Rapid device-miniaturization keeps on inducing challenges in building energy efficient microprocessors. As the size of the transistors continuously decreasing, more uncertainties emerge in their operations. On the other hand, integrating more and more transistors on a single chip accentuates the need to lower its supply-voltage. This dissertation investigates one of the primary device uncertainties - timing error, in microprocessor performance bottleneck in NTC era. Then it proposes various innovative techniques to exploit these opportunities to maintain processor energy efficiency, in the context of emerging challenges. Evaluated with the cross-layer methodology, the proposed approaches achieve substantial improvements in processor energy efficiency, compared to other start-of-art techniques.
Checksum
cdae335f3e83caae3ddbed2197a4d015
Recommended Citation
Chen, Hu, "Exploiting Adaptive Techniques to Improve Processor Energy Efficiency" (2016). All Graduate Theses and Dissertations. 4985.
https://digitalcommons.usu.edu/etd/4985
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