Date of Award:
5-2011
Document Type:
Thesis
Degree Name:
Master of Science (MS)
Department:
Electrical and Computer Engineering
Committee Chair(s)
Paul Israelsen
Committee
Paul Israelsen
Committee
Jacob Gunther
Committee
Reyhan Baktur
Abstract
The integral image representation of an image is important for a large number of modern image processing algorithms. Integral image representations can reduce computation and increase the operating speed of certain algorithms, improving real-time performance. Due to increasing demand for real-time image processing performance, an integral image architecture capable of accelerating the calculation based on the amount of available resources is presented. Use of the proposed accelerator allows for subsequent stages of a design to have data sooner and execute in parallel. It is shown here how, with some additional resources used in the Field Programmable Gate Array (FPGA), a speed increase is obtained by using a one-dimensional Systolic Array (SA) approach. Additionally, extra guidelines are given for further research in this area.
Checksum
b896983df1a5fbf3a9d3f7d06a610810
Recommended Citation
De la Cruz, Juan Alberto, "Field-Programmable Gate Array Implementation of a Scalable Integral Image Architecture Based on Systolic Arrays" (2011). All Graduate Theses and Dissertations, Spring 1920 to Summer 2023. 854.
https://digitalcommons.usu.edu/etd/854
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Comments
This work made publicly available electronically on February 14, 2011.