Date of Award:


Document Type:


Degree Name:

Master of Science (MS)


Electrical and Computer Engineering

Committee Chair(s)

Koushik Chakraborty


Koushik Chakraborty


Sanghamitra Roy


Zhen Zhang


Artificial Intelligence (AI) is one of the biggest fields of research for computer hardware right now. Hardware accelerators are chips (such as graphics cards) that are purpose built to be the best at a specific type of operation. AI hardware accelerators are a growing field of research. Part of hardware in general is a digital clock that controls the pace at which computations occur. If this clock runs too quickly, the hardware won't have enough time to finish its computation. We call that a timing error. This paper focuses on studying the characteristics of timing errors in a small custom AI hardware accelerator design on a device called an FPGA (Field Programmable Gate Array). An FPGA is a sort of re-configurable hardware platform that allows for much cheaper prototyping than manufacturing a custom design in a physical chip (which would cost millions of dollars at least). By running the experiment on exactly one FPGA board, the experiment will control for any microscopic flaws in that specific board (called Process Variation or PV). Without this control, the small differences in computation that are observed could be attributed to PV. The experiment consists of loading the design onto the FPGA and sweeping the clock from its normal operating frequency up to more than 3× the normal frequency the design is intended to run at. During each sweep, the outputs of the computation are captured for later analysis.



Creative Commons License

Creative Commons Attribution 4.0 License
This work is licensed under a Creative Commons Attribution 4.0 License.