Today the scanning electron microscope has become the tool for investigations on integrated circuits. In e-beam testing ore-beam reconfiguration of VLSI, the effective charging conditions of top oxides are important. However due to the insulator nature of the zone impinged by the electrons, it is generally difficult to obtain quantitative information. Here we present and illustrate the use of floating gate MOS transistors for charging determination. The basic equations are derived from a physical model and a comparison is made with the evolution of the electrical characteristics of the devices under charge deposition. The effective charging yields are determined in the 2-6 keV region. The effect of topography on surface charge exchanges is shown to lead to an agreement between experiment and theory. This method appears to be very sensitive and easy to implement in the case of integrated circuits studies.
"The Floating Gate Metal Oxide Semiconductor Transistor, A Device for Low kV E-Beam Charging Evaluations,"
Scanning Microscopy: Vol. 2
, Article 15.
Available at: https://digitalcommons.usu.edu/microscopy/vol2/iss4/15