Date of Award:
5-2015
Document Type:
Dissertation
Degree Name:
Doctor of Philosophy (PhD)
Department:
Electrical and Computer Engineering
Committee Chair(s)
Koushik Chakraborty
Committee
Koushik Chakraborty
Committee
Sanghamitra Roy
Committee
Todd Moon
Committee
Chris Winstead
Committee
Dan Watson
Abstract
The trend towards massive parallel computing has necessitated the need for an On-Chip communication framework that can scale well with the increasing number of cores. At the same time, technology scaling has made transistors susceptible to a multitude of reliability issues. This dissertation demonstrates design techniques that address both reliability and security issues facing modern NoC architectures. The reliability and security problem is tackled at different abstraction levels using a series of schemes that combine information from the architecture-level as well as hardware-level in order to combat aging effects and meet secure design stipulations while maintaining modest power-performance overheads.
Checksum
f86c14787f8068d5029bb3334e8d13a6
Recommended Citation
Ancajas, Dean Michael B, "Design of Reliable and Secure Network-On-Chip Architectures" (2015). All Graduate Theses and Dissertations, Spring 1920 to Summer 2023. 4150.
https://digitalcommons.usu.edu/etd/4150
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