Date of Award:

5-2016

Document Type:

Thesis

Degree Name:

Master of Science (MS)

Department:

Electrical and Computer Engineering

Committee Chair(s)

Thidapat Chantem

Committee

Thidapat Chantem

Committee

Koushik Chakraborty

Committee

Ryan Gerdes

Abstract

Embedded devices are computer systems with a dedicated function, such as kitchen appliances, electronic toys, phones, et cetera. Embedded devices are commonplace, and many are expected to respond to users in real-time. Such devices are often categorized as real-time embedded systems as they differ from other embedded systems in that work performed by a real-time embedded system must be scheduled such that timeliness can be provided to the user (e.g. when someone is talking on a phone, the phone needs to be able to schedule the sending and receiving of data in a timely manner such that the conversation is intelligible). Further, for real-time embedded systems that perform life-critical functions (e.g. medical equipment, avionics instruments, military devices, et cetera), scheduling must be able to guarantee that all of the work can be performed in the required amount of time. These systems are often referred to as Hard Real-Time Systems (HRTS).

Due to the increase in popularity of multi-core processors, many real-time embedded systems have transitioned from a single core processor architecture to a multi-core architecture. Unfortunately, similar to how scheduling tasking for a group of people is more complicated than scheduling tasking for just one person, the transition to a multi-core architecture has proven to be a difficult problem for scheduling.

Further, energy efficiency is a major design metric in many HRTS, and to obtain energy savings, most embedded systems use dynamic voltage and frequency scaling (DVFS). With DVFS, the processing cores on the multi-core processor can increase and decrease its voltage and frequency to change its energy consumption. Although reducing the voltage and frequency also reduces the amount of work that can be accomplished, typically the relationship between work and energy consumption is quadratic such that reducing the frequency by two reduces energy consumption by four. As such when a processing core only has a little bit of work to be completed, the voltage and frequency can be reduced to allow the core to operate slower and consume significantly less energy. Conversely, when the workload is high, the core can increase its voltage and frequency to be able to meet its schedule. Unfortunately, as clock frequencies have increased and transistors have gotten smaller, being able to implement DVFS in a multi-core processor has gotten more difficult. To mitigate this difficulty, multi-core processors often use a voltage and frequency island (VFI) to implement DVFS, where multiple processing cores reside on a single VFI. Although a VFI does simplify the implementation of DVFS on a multi-core processor, it also causes that all of the cores on the VFI must operate at the same voltage and frequency; which further complicates scheduling.

To be able to guarantee scheduling for HRTS in an energy efficient manner in the presence of VFI, we propose EDF-hv. Simulation results revealed that, when applied correctly, EDF-hv can reduce system energy consumption by 15.9% on average and up to 61.6%.

Checksum

1264bbc3209201019752fbd07139b2d8

Download

Share

COinS

Copyright for this work is retained by the student. If you have any questions regarding the inclusion of this work in the Digital Commons, please email us at .