Date of Award:
12-2010
Document Type:
Thesis
Degree Name:
Master of Science (MS)
Department:
Electrical and Computer Engineering
Committee Chair(s)
Jacob Gunther
Committee
Jacob Gunther
Committee
Koushik Chakraborty
Committee
Todd Moon
Abstract
Processing power is a key technical challenge holding back the development of a high-performance software defined radio (SDR). Traditionally, SDR has utilized digital signal processors (DSPs), but increasingly complex algorithms, higher data rates, and multi-tasking needs have exceed the processing capabilities of modern DSPs. Reconfigurable computers, such as field-programmable gate arrays (FPGAs), are popular alternatives because of their performance gains over software for streaming data applications like SDR. However, FPGAs have not yet realized the ideal SDR because architectures have not fully utilized their partial reconfiguration (PR) capabilities to bring needed flexibility. A reconfigurable processor architecture is proposed that utilizes PR in reconfigurable computers to achieve a more sophisticated SDR. The proposed processor contains run-time swappable blocks whose parameters and interconnects are programmable. The architecture is analyzed for performance and flexibility and compared with available alternate technologies. For a sample QPSK algorithm, hardware performance gains of at least 44x are seen over modern desktop processors and DSPs while most of their flexibility and extensibility is maintained.
Checksum
582400e7eac0499c5653075ea4e77515
Recommended Citation
Templin, Joshua R., "Design of an Adaptable Run-Time Reconfigurable Software-Defined Radio Processing Architecture" (2010). All Graduate Theses and Dissertations, Spring 1920 to Summer 2023. 810.
https://digitalcommons.usu.edu/etd/810
Copyright for this work is retained by the student. If you have any questions regarding the inclusion of this work in the Digital Commons, please email us at .
Comments
This work made publicly available electronically on December 23, 2010.