Location
Salt Lake Community College Student Center
Start Date
5-4-2009 2:30 PM
Description
Triple Modular Redundancy (TMR) is a common reliability technique for FPGA designs used in radiation environments. TMR consists of triplicating a design and inserting voters to mask errors using redundancy. This paper will investigate the automatic placement of voters in TMR designs. In particular, it will introduce three algorithms for determining where to insert synchronization voters and compare the area and timing impact of these algorithms on FPGA designs. It will be shown that the placement of synchronization voters in a triplicated design can have an important impact on the area and timing characteristics of the resulting design. The algorithms presented in this paper give results that increase the critical path length of a design when adding TMR voters by as little as 3% to as much as 50%.
Voter Insertion Techniques for Fault Tolerant FPGA Design
Salt Lake Community College Student Center
Triple Modular Redundancy (TMR) is a common reliability technique for FPGA designs used in radiation environments. TMR consists of triplicating a design and inserting voters to mask errors using redundancy. This paper will investigate the automatic placement of voters in TMR designs. In particular, it will introduce three algorithms for determining where to insert synchronization voters and compare the area and timing impact of these algorithms on FPGA designs. It will be shown that the placement of synchronization voters in a triplicated design can have an important impact on the area and timing characteristics of the resulting design. The algorithms presented in this paper give results that increase the critical path length of a design when adding TMR voters by as little as 3% to as much as 50%.