Location

Utah State University

Start Date

5-11-2011 10:45 AM

Description

This paper demonstrates the ability to reuse arbitrary IP as primitive cores in architectural synthesis algorithms for FPGA by encapsulating these IP in meta-data. This metadata is represented as a set of extensions to the IP-XACT XML specification and defines the high-level data types and the temporal behavior of IP. This paper describes how these extensions are used in the Ogre synthesis system to facilitate automatic synthesis of control and interface logic for homogeneous synchronous dataflow (H-SDF) designs.

Download

Share

COinS
 
May 11th, 10:45 AM

Meta-Data-Enabled Reuse of Dataflow Intellectual Property for FPGAs

Utah State University

This paper demonstrates the ability to reuse arbitrary IP as primitive cores in architectural synthesis algorithms for FPGA by encapsulating these IP in meta-data. This metadata is represented as a set of extensions to the IP-XACT XML specification and defines the high-level data types and the temporal behavior of IP. This paper describes how these extensions are used in the Ogre synthesis system to facilitate automatic synthesis of control and interface logic for homogeneous synchronous dataflow (H-SDF) designs.