Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip
Formal Methods for Industrial Critical System
A fault-tolerant routing algorithm in Network-on-Chip architectures provides adaptivity for on-chip communications. Adding fault-tolerance adaptivity to a routing algorithm increases its design complexity and makes it prone to deadlock and other problems
Z. Zhang , W. Serwe, J. Wu, T. Yoneda, H. Zheng, and C. Myers, “Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip ”, 19th International Workshop on Formal Methods for Industrial Critical Systems, Sep, 2014.
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