Title

Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip

Document Type

Poster

Journal/Book Title/Conference

Formal Methods for Industrial Critical System

Volume

8718

Publisher

Cham Springer

Publication Date

9-1-2014

First Page

48

Last Page

62

DOI

10.1007/978-3-319-10702-8_4

Abstract

A fault-tolerant routing algorithm in Network-on-Chip architectures provides adaptivity for on-chip communications. Adding fault-tolerance adaptivity to a routing algorithm increases its design complexity and makes it prone to deadlock and other problems

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