Document Type

Conference Paper

Journal/Book Title/Conference

NOCS '15: Proceedings of the 9th International Symposium on Networks-on-Chip


Association for Computing Machinery

Publication Date



National Science Foundation


In this paper, we propose a covert threat model for MPSoCs designed using 3rd party Network-on-Chips (NoC). We illustrate that a malicious NoC can disrupt the availability of on-chip resources, thereby causing large performance bottlenecks for the software running on the MPSoC platform. We then propose a runtime latency auditor that enables an MPSoC integrator to monitor the trustworthiness of the deployed NoC throughout the chip lifetime. For the proposed technique, our comprehensive cross-layer analysis indicates modest overheads of 12.73% in area, 9.844% in power and 5.4% in terms of network latency.


© 2015. This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in NOCS '15: Proceedings of the 9th International Symposium on Networks-on-Chip,