A Global Router on GPU Architecture
2013 IEEE 31st International Conference on Computer Design, ICCD 2013
Institute of Electrical and Electronics Engineers
In the modern VLSI design flow, global router is often utilized to provide fast and accurate congestion analysis for upstream processes to improve the design routability. Global routing parallelization is a good candidate to speedup its runtime performance while delivering very competitive solution quality. In this paper, we first study the cause of insufficient exploitable concurrency of the existing net level concurrency model, which has become a major bottleneck for parallelizing the emerging design problems. Then, we mitigate this limitation with a novel fine grain parallel model, with which a GPU based multi-agent global router is designed. Our experimental results indicate that the parallel model can effectively support the GPU based global router, and deliver stable solutions. The runtime comparison with NCTUgr2 has shown that upto 3.9x speedup is achieved by the GPU based router. © 2013 IEEE.
Yiding Han, Koushik Chakraborty, and Sanghamitra Roy, A Global Router on GPU Architecture. IEEE International Conference on Computer Design (ICCD), pp. 78-84, October 2013, Asheville, NC.