HCI-Tolerant NoC Router Microarchitecture
Proceedings of the 50th Annual Design Automation Conference
Association for Computing Machinery
National Science Foundation
The trend towards massive parallel computing has necessitated the need for an On-Chip communication framework that can scale well with the increasing number of cores. At the same time, technology scaling has made transistors susceptible to a multitude of reliability issues (NBTI, HCI, TDDB). In this work, we propose an HCI-Tolerant microarchitecture for an NoC Router by manipulating the switching activity around the circuit. We find that most of the switch- ing activity (the primary cause of HCI degradation) are only concentrated in a few parts of the circuit, severely degrading some portions more than others. Our techniques increase the lifetime of an NoC router by balancing this switching activity. Compared to an NoC without any reliability techniques, our best schemes improve the switching activity dis- tribution, clock cycle degradation, system performance and energy delay product per flit by 19%, 26%, 11% and 17%, respectively, on an average. Copyright © 2013 ACM.
Dean Michael Ancajas, James McCabe Nickerson, Koushik Chakraborty and Sanghamitra Roy, HCI Tolerant NoC Router Micro-architecture. IEEE/ACM Design Automation Conference (DAC), Article 40, June 2013, Austin, TX.