Document Type

Article

Journal/Book Title/Conference

Journal of Hardware and Systems Security

Publisher

Springer

Publication Date

5-30-2017

First Page

173

Last Page

187

Abstract

Network-on-chip facilitates glueless interconnection of various on-chip components in the forthcoming system-on-chips. As in the case of any new technology, security is a major concern in network-on-chip (NoC) design too. In this work, we explore a covert threat model for multiprocessor system-on-chips (MPSoCs) stemming from the use of malicious third-party network-on-chips (NoCs). We illustrate that a rogue NoC (rNoC) can selectively disrupt the perceived availability of on-chip resources, thereby causing large performance bottlenecks for the applications running on the MPSoC platform. Further, to counter the threat posed by rNoC, we propose a runtime latency auditor that enables an MPSoC integrator to monitor the trustworthiness of the deployed NoC throughout the chip lifetime. We also discuss measures that can be taken to minimize the impact of a rNoC, once it is detected. Our comprehensive cross-layer analysis of our novel detection technique indicates modest overheads of 12.73% in area, 9.844% in power, and 5.4% in terms of network latency.

Comments

This version of the article has been accepted for publication, after peer review (when applicable) and is subject to Springer Nature’s AM terms of use, but is not the Version of Record and does not reflect post-acceptance improvements, or any corrections. The Version of Record is available online at: http://dx.doi.org/10.1007/s41635-017-0008-z

Download

Share

COinS