IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Institute of Electrical and Electronics Engineers
National Science Foundation
With aggressive technology scaling, the complexity of the global routing problem is poised to grow rapidly. Solving such a large computational problem demands a high-throughput hardware platform such as modern graphics processing units (GPUs). In this paper, we explore a hybrid GPU-CPU high-throughput computing environment as a scalable alternative to the traditional CPU-based router. We introduce net-level concurrency (NLC), which is a novel parallel model for router algorithms and aims to exploit concurrency at the level of individual nets. To efficiently uncover NLC, we design a scheduler to create groups of nets that can be routed in parallel. At its core, our scheduler employs a novel algorithm to dynamically analyze data dependencies between multiple nets. We believe such an algorithm can lay the foundation for uncovering data-level parallelism in routing, which is a necessary requirement for employing high-throughput hardware. Detailed simulation results show an average of 4× speedup over NTHU-Route 2.0 with negligible loss in solution quality. To the best of our knowledge, this is the first work on utilizing GPUs for global routing.
Yiding Han, Dean Michael Ancajas, Koushik Chakraborty and Sanghamitra Roy, Exploring High Throughput Computing Paradigm for Global Routing, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 55-67, Vol. 22, Issue 1, January 2014.