Date of Award:
5-2015
Document Type:
Thesis
Degree Name:
Master of Science (MS)
Department:
Electrical and Computer Engineering
Committee Chair(s)
Sanghamitra Roy
Committee
Sanghamitra Roy
Committee
Koushik Chakraborty
Committee
Zeljjko Pantic
Abstract
Historically, the increase of transistor devices per area of chip has been one of the key drivers of microprocessor performance. While the transistor count per chip keeps increasing, today’s microprocessor power budget limits the number of devices that can be turned on. This issue stems from the fact that new device technologies dissipate more power in form of heat—a problem that can cause circuit breakdown due to excessive temperatures.
Near-Threshold Computing (NTC), where the operating voltage is reduced near the threshold voltage that turns on a transistor, is a popular research topic. NTC significantly reduces the power consumption and allows a higher number of devices to be used given a certain power budget. Although it is energy efficient, NTC suffers from a high rate of circuit failures induced by both manufacturing imperfections and the operating environment. Static Random Access Memory (SRAM) arrays are the most affected components of a microprocessor, and consequently require robust design techniques. This thesis proposes a technique that exploits the software use of SRAM arrays in order to reduce circuit failure in NTC.
Checksum
2589ac1d5faea2fc349f1bb25bfcce29
Recommended Citation
Mugisha, Dieudonne Manzi, "Exploiting Application Behaviors for Resilient Static Random Access Memory Arrays in the Near-Threshold Computing Regime" (2015). All Graduate Theses and Dissertations. 4550.
https://digitalcommons.usu.edu/etd/4550
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