Date of Award:
12-2009
Document Type:
Thesis
Degree Name:
Master of Science (MS)
Department:
Electrical and Computer Engineering
Committee Chair(s)
Aravind Dasu
Committee
Aravind Dasu
Committee
Brandon Eames
Committee
Scott Budge
Abstract
The design of a common architecture that can support multiple data-flow patterns (or contexts) embedded in complex control flow structures, in applications like multimedia processing, is particularly challenging when the target platform is a Field Programmable Gate Array (FPGA) with a heterogeneous mixture of device primitives. This thesis presents scheduling and mapping algorithms that use a novel area cost metric to generate resource aware context adaptable architectures. Results of a rigorous analysis of the methodology on multiple test cases are presented. Results are compared against published techniques and show an area savings and execution time savings of 46% each.
Checksum
7834c633b40dc66a56d5e41c0e8a4a3a
Recommended Citation
Samala, Harikrishna, "Methodology to Derive Resource Aware Context Adaptable Architectures for Field Programmable Gate Arrays" (2009). All Graduate Theses and Dissertations. 484.
https://digitalcommons.usu.edu/etd/484
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