Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Baising Algorithm
The current version of this paper is available at: http://digitalcommons.usu.edu/etd/1419/
Large dense structures like DRAMs (Dynamic Random Access Memory) are particu- larly susceptible to process variation, which can lead to variable latencies in different mem- ory arrays. However, very little work exists on variation studies in DRAMs. This is due to the fact that DRAMs were traditionally placed off-chip and their latency changes due to pro- cess variation did not impact the overall processor performance. However, emerging technol- ogy trends like three-dimensional integration, use of sophisticated memory controllers, and continued scaling of technology node, substantially reduce DRAM access latency. Hence, future technology nodes will see widespread adoption of embedded DRAMs. This makes process variation a critical upcoming challenge in DRAMs that must be addressed in cur- rent and forthcoming technology generations. In this paper, techniques for modeling the effect of random, as well as spatial variation, in large DRAM array structures are presented. Sensitivity-based gate level process variation models combined with statistical timing anal- ysis are used to estimate the impact of process variation on the DRAM performance and leakage power. A simulated annealing-based Vth assignment algorithm using adaptive body biasing is proposed in this thesis to improve the yield of DRAM structures. By applying the algorithm on a 1GB DRAM array, an average of 14.66% improvement in the DRAM yield is obtained.