Location

Orbital ATK Conference Center

Start Date

5-7-2018 9:20 AM

Description

Field programmable gate arrays (FPGAs) offer large amounts of configurable logic for use in a wide variety of applications, including space-based missions. Radiation-induced configuration upsets can cause deployed designs to fail. This work demonstrates the application of partial triple modular redundancy (pTMR) on a commercial FPGA-based networking system to improve overall soft-error rate (SER). Applying pTMR to this system increased the size of the FPGA circuit by 2.8%. Accelerated neutron testing was performed to measure the baseline failure rate as well as the improvement with pTMR. The measured failure rate of the unmitigated baseline system was estimated at 135 FIT. The mitigated system had a reduced failure rate of 22 FIT (approximately a 6x improvement). This work demonstrates improvement in the SER of a commercial FPGA-based design using an automated post-synthesis mitigation technique and a small amount of additional logic resources.

Comments

Session 1

Available for download on Tuesday, May 07, 2019

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May 7th, 9:20 AM

Partial Triple Modular Redundancy: Low-Cost Resilience for FPGAs in Space Environments

Orbital ATK Conference Center

Field programmable gate arrays (FPGAs) offer large amounts of configurable logic for use in a wide variety of applications, including space-based missions. Radiation-induced configuration upsets can cause deployed designs to fail. This work demonstrates the application of partial triple modular redundancy (pTMR) on a commercial FPGA-based networking system to improve overall soft-error rate (SER). Applying pTMR to this system increased the size of the FPGA circuit by 2.8%. Accelerated neutron testing was performed to measure the baseline failure rate as well as the improvement with pTMR. The measured failure rate of the unmitigated baseline system was estimated at 135 FIT. The mitigated system had a reduced failure rate of 22 FIT (approximately a 6x improvement). This work demonstrates improvement in the SER of a commercial FPGA-based design using an automated post-synthesis mitigation technique and a small amount of additional logic resources.