Document Type
Conference Paper
Journal/Book Title/Conference
Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Publisher
Institute of Electrical and Electronics Engineers
Publication Date
3-14-2016
Funder
National Science Foundation
First Page
1461
Last Page
1464
Abstract
Network-on-Chip (NoC) has become the de-facto standard for on-chip communication in MPSoCs. The growing NoC power footprint, increase in the transistor current, and high switching speed of the logic devices, exacerbate the peak power supply noise (PSN) in the NoC power delivery network (PDN). Hence, preserving power supply integrity in the NoC PDN is critical. In this work, we propose PRADA (PSN-aware Runtime Adaptation)-a collection of a novel flow-control protocol (PAF) and an adaptive routing algorithm (PAR), to mitigate PSN in NoCs. Our best scheme achieves 14% and 12% improvements in the regional peak PSN and energy efficiency, with an average of 4.6% performance overhead and marginal area and power footprints.
Recommended Citation
Prabal Basu, Rajesh JayashankaraShridevi, Koushik Chakraborty and Sanghamitra Roy, PRADA: Combating Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms. Proceedings of the IEEE/ACM Design Automation and Test in Europe (DATE), pp. 46-464, March 2016, Dresden, Germany.
Comments
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