2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
Institute of Electrical and Electronics Engineers
National Science Foundation
Aggressive technology scaling exacerbates the problem of voltage emergencies in emerging MPSoC systems. Network-on-Chips, the de-facto standard for connecting on-chip components in forthcoming devices play a central role in providing robust and reliable communication. In this work, we propose DrNoC (droop resilient network-on-chip)-two microarchitectural techniques to mitigate voltage emergency-induced timing errors in NoCs and preserve error-free communication throughout the network. DrNoC employs frequency downscaling and a pipeline error-recovery mechanism to reclaim corrupted flits in the router. Compared to the recently proposed NSFTR fault-tolerant technique, DrNoC offers a 27% improvement in energy-delay efficiency.
Rajesh JayashankaraShridevi, Dean Michael Ancajas, Koushik Chakraborty and Sanghamitra Roy, Tackling Voltage Emergencies in NoC Through Timing Error Resilience. Proceedings of the IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp. 04-09, July 2015, Rome, Italy.
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