Title

Tackling Voltage Emergencies in NoC Through Timing Error Resilience.

Document Type

Conference Paper

Journal/Book Title/Conference

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

Publisher

Institute of Electrical and Electronics Engineers

Publication Date

7-22-2015

Funder

National Science Foundation

First Page

104

Last Page

109

Abstract

Aggressive technology scaling exacerbates the problem of voltage emergencies in emerging MPSoC systems. Network-on-Chips, the de-facto standard for connecting on-chip components in forthcoming devices play a central role in providing robust and reliable communication. In this work, we propose DrNoC (droop resilient network-on-chip)-two microarchitectural techniques to mitigate voltage emergency-induced timing errors in NoCs and preserve error-free communication throughout the network. DrNoC employs frequency downscaling and a pipeline error-recovery mechanism to reclaim corrupted flits in the router. Compared to the recently proposed NSFTR fault-tolerant technique, DrNoC offers a 27% improvement in energy-delay efficiency.

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