Resilient Cache Design for Mobile Processors in the Near-Threshold Regime

Authors

Dieudonne Manzi Mugisha, Utah State University
Hu Chen, Utah State UniversityFollow
Sanghamitra Roy, Utah State UniversityFollow
Koushik Chakraborty, Utah State UniversityFollow

Document Type

Article

Journal/Book Title/Conference

Journal of Low Power Electronics

Volume

11

Issue

2

Publisher

American Scientific Publishers

Publication Date

6-1-2015

First Page

112

Last Page

120

Abstract

Near-threshold computing embodies an intriguing choice for extending mobile processor battery life due to its high energy efficiency. However, process, voltage and temperature variations cause a significantly high failure rate of level 1 cache SRAM cells in the near-threshold regime compared to the super-threshold regime. In this work, we show that faulty cells in the near-threshold regime are highly clustered in certain regions of the cache. We then propose a low overhead technique to dynamically reduce the performance penalty due to process variations by exploiting the spatial congregation of faulty cells and application cache behaviors. Our experimental results demonstrate up to 78% reduction in performance loss over two state-of-art techniques.

Recommended Citation

Dieudonne Manzi Mugisha, Hu Chen, Sanghamitra Roy and Koushik Chakraborty, Resilient Cache Design for Mobile Processors in the Near-Threshold Regime, Journal of Low Power Electronics (JOLPE), pp. 2-20, Vol. , No. 2, June 2015.