DARP: Dynamically Adaptable Resilient Pipeline Design in Microprocessors
Document Type
Conference Paper
Journal/Book Title/Conference
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Publisher
I E E E Computer Society
Publication Date
3-24-2014
Abstract
In this paper, we demonstrate that the sensitized path delays in various microprocessor pipe stages exhibit intriguing temporal and spatial variations during the execution of real world applications. To effectively exploit these delay variations, we propose Dynamically Adaptable Resilient Pipeline (DARP)-a series of runtime techniques to boost power performance efficiency and fault tolerance in a pipelined microprocessor. DARP employs early error prediction to avoid a major portion of the timing errors. Using a rigorous circuit-architectural infrastructure, we demonstrate substantial improvements in the performance (9.4-20%) and energy efficiency (6.4-27.9%), compared to state-of-the-art techniques. © 2014 EDAA.
Recommended Citation
Hu Chen, Sanghamitra Roy and Koushik Chakraborty, DARP: Dynamically Adaptable Resilient Pipeline Design in Microprocessors. IEEE/ACM Design Automation and Test in Europe (DATE), Article No. 62, March 2014, Dresden, Germany.
