Document Type
Article
Journal/Book Title/Conference
Journal of Low Power Electronics and Applications
Volume
10
Issue
4
Publisher
MDPI AG
Publication Date
10-16-2020
Funder
National Science Foundation
First Page
1
Last Page
19
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Abstract
AI evolution is accelerating and Deep Neural Network (DNN) inference accelerators are at the forefront of ad hoc architectures that are evolving to support the immense throughput required for AI computation. However, much more energy efficient design paradigms are inevitable to realize the complete potential of AI evolution and curtail energy consumption. The Near-Threshold Computing (NTC) design paradigm can serve as the best candidate for providing the required energy efficiency. However, NTC operation is plagued with ample performance and reliability concerns arising from the timing errors. In this paper, we dive deep into DNN architecture to uncover some unique challenges and opportunities for operation in the NTC paradigm. By performing rigorous simulations in TPU systolic array, we reveal the severity of timing errors and its impact on inference accuracy at NTC. We analyze various attributes—such as data–delay relationship, delay disparity within arithmetic units, utilization pattern, hardware homogeneity, workload characteristics—and uncover unique localized and global techniques to deal with the timing errors in NTC.
Recommended Citation
Pramesh Pandey, Noel Gundi, Prabal Basu, Tahmoures Shabanian, Mitchell Patrick, Koushik Chakraborty and Sanghamitra Roy, Challenges and Opportunities in Near Threshold DNN Accelerators around Timing Errors, Journal of Low Power Electronics and Applications (JLPEA), Volume 0, Issue 4, pp. 33, October 2020.
