Document Type
Article
Journal/Book Title/Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume
23
Issue
2
Publisher
Institute of Electrical and Electronics Engineers
Publication Date
2-1-2015
First Page
369
Last Page
373
Abstract
Continuous technology scaling has made aging mechanisms, such as negative bias temperature instability and electromigration primary concerns in network-on-chip (NoC) designs. In this paper, we extensively analyze the effects of these aging mechanisms on NoC routers and links. We observe a critical need of a robust aging-aware routing algorithm that not only reduces power-performance overheads caused due to aging degradation, but also minimizes the stress experienced by heavily utilized routers and links. To solve this problem, we propose an aging-aware adaptive routing algorithm and a router microarchitecture that routes the packets along the paths, which are both least congested and experience minimum aging degradation. After an extensive experimental analysis using real workloads, we observe 13% and 12.17% average overhead reduction in network latency and energy-delay product per flit, a 10.4% improvement in performance, and a 60% improvement in mean time to failure using our aging-aware routing algorithm.
Recommended Citation
Dean Michael Ancajas, Kshitij Bhardwaj, Koushik Chakraborty and Sanghamitra Roy, Wearout Resilience in NoCs through an Aging Aware Adaptive Routing Algorithm, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Volume 23, Issue 2, pp. 369-373, February 2015.
