Date of Award:
8-2018
Document Type:
Thesis
Degree Name:
Master of Science (MS)
Department:
Electrical and Computer Engineering
Committee Chair(s)
Koushik Chakraborty
Committee
Koushik Chakraborty
Committee
Sanghamitra Roy
Committee
Amanda Lee Hughes
Abstract
Over the last decade, Graphics Processing Units (GPUs) have been used extensively in gaming consoles, mobile phones, workstations and data centers, as they have exhibited immense performance improvement over CPUs, in graphics intensive applications. Due to their highly parallel architecture, general purpose GPUs (GPGPUs) have gained the foreground in applications where large data blocks can be processed in parallel. However, the performance improvement is constrained by a large power consumption. Likewise, Near Threshold Computing (NTC) has emerged as an energy-efficient design paradigm. Hence, operating GPUs at NTC seems like a plausible solution to counteract the high energy consumption. This work investigates the challenges associated with NTC operation of GPUs and proposes a low-power GPU design, Split Latency Allocator, to sustain the performance of GPGPU applications.
Checksum
5f1da655ecb32d32319ef212fa96d567
Recommended Citation
Pal, Asmita, "Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit" (2018). All Graduate Theses and Dissertations, Spring 1920 to Summer 2023. 7155.
https://digitalcommons.usu.edu/etd/7155
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