Date of Award:
5-2023
Document Type:
Thesis
Degree Name:
Master of Science (MS)
Department:
Electrical and Computer Engineering
Committee Chair(s)
Zhen Zhang
Committee
Zhen Zhang
Committee
Arnd Hartmanns
Committee
Sanghamitra Roy
Abstract
Modeling physical systems with formal analysis tools can help in the design of more fault-proof systems, by helping to determine if unpredictable or unwanted behavior may occur. Probabilistic verification further advances such processes, by providing quantitative information about the system. More complex systems can especially benefit from formal modeling and verification, as testing the physical system in every possible condition manually, can be extremely complex, and often impossible.
There is a growing interest in the application of Network-on-Chip (NoC) systems. NoCs can help simplify communication between the subsystems of many technologies, including the ever more complex multicore processors being produced. These NoCs come with their own problems, and under high network activity, can cause power fluctuations on the chip’s power supply. These fluctuations can cause data corruption and loss, resulting in reduced performance, and even unpredictable behavior.
This work presents a novel approach to creating a modular probabilistic model of an NoC, which can be scaled to meet the needs of a variety of implementations. Additionally, it presents a structured approach for ensuring that NoC models are indeed representative of their physical counterparts.
Checksum
8c7e3de98abcbc962d9cabb7f2c7eb7f
Recommended Citation
Boe, Jonah W., "Probabilistic Verification for Modular Network-on-Chip Systems" (2023). All Graduate Theses and Dissertations, Spring 1920 to Summer 2023. 8763.
https://digitalcommons.usu.edu/etd/8763
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