Date of Award:
8-2026
Document Type:
Thesis
Degree Name:
Master of Science (MS)
Department:
Electrical and Computer Engineering
Committee Chair(s)
Zhen Zhang
Committee
Zhen Zhang
Committee
Arnd Hartmanns
Committee
Sanghamitra Roy
Committee
Honjie Wang
Abstract
To satisfy increasing demands for computer chip performance in personal computing, mobile devices, and commercial server computing, a modern computer chip is constructed with tens (or hundreds) of small individual computing modules. Each of these modules must communicate with one other to share information about the running state of a computer. Historically, when chips were a few modules a simple communication method sufficied. However, as the number of modules in a chip grew, a more effecient method was needed in order to maintain performance across the system as a whole. A Network-on-Chip (NoC) design is the de-facto communication method for chips with many components because it is effecient, performant, and scalable. NoC designs are more complex than historical designs and require in-depth testing, analysis, and verification to ensure that they function correctly. Not only do NoC designs need to function correctly, but they also must be rigorously analyzed in regards to their reliability. While testing provides a measure of confidence in a design, analysis of a system using mathematical methods, i.e., formal verification, provides strong guarantees that a system functions correctly and demonstrates specific reliability characteristics. This thesis first presents a formal analysis of the functional correctness of a mesh-style NoC design, and the provides a formal analysis of the reliability of that design in regard to electrical noise in the system. These contributions entail a NoC model that is highly flexible, scalable, and provably correct. This model will assist computer engineers in the creation of reliable and correct NoCs.
Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
Waddoups, Nicholas, "Modular Verification for Network-On-Chip Designs Using Probabilistic Verification and Assume-Guarantee Reasoning" (2026). All Graduate Theses and Dissertations, Fall 2023 to Present. 816.
https://digitalcommons.usu.edu/etd2023/816
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