Session
Technical Session V: Subsystems
Abstract
A miniaturized, low-power parallel processor for space applications is under development by Space Computer Corporation for DARPA's Advanced Space Technology Program. The basic goal of this project is the reduction, by an order of magnitude or more, of on-board processor weight, size and power consumption for space-based sensor systems. Our approach for achieving this goal is to use low power VLSI devices which maximize throughput per watt, together with three dimensional hybrid wafer-scale integration and packaging technology. In its prototype version, a l2-node processor will have a peak throughput greater than 1.2 GFLOPS and occupy a volume less than 15 cubic inches.
Miniaturized, Low-Power Parallel Processor for Space Applications
A miniaturized, low-power parallel processor for space applications is under development by Space Computer Corporation for DARPA's Advanced Space Technology Program. The basic goal of this project is the reduction, by an order of magnitude or more, of on-board processor weight, size and power consumption for space-based sensor systems. Our approach for achieving this goal is to use low power VLSI devices which maximize throughput per watt, together with three dimensional hybrid wafer-scale integration and packaging technology. In its prototype version, a l2-node processor will have a peak throughput greater than 1.2 GFLOPS and occupy a volume less than 15 cubic inches.
