Session
Technical Session VI: Attitude Control Systems
Abstract
A high-performance processor circuit called the SC-3 has been developed to meet the requirements of advanced experiment and attitude control applications. It is based on the 16 MHz Intel 80386/80387 chip set and implements a dual bus system configuration which allows high-speed, 32-bit wide memory and low-speed. 16-bit wide Input Output(I/O) circuits to be separated. This separation maintains compatibility with a wide range of current I/O circuit designs while exploiting the high-bandwidth memory access capabilities of the 80386. Performance is further enhanced by means of a cache on the 32-bit bus. Gibson, Whetstone, and Dhrystone instruction mixes have been used to evaluate performance under various operating modes. When the SC-3 is constrained to execute from 16-bit memory. the Gibson mix indicates a 32% performance improvement compared to previous 16-bit processors. An average of 1.1 million Whetstones per second are performed over the typical range of memory wait states. The average Dhrystone performance improvement between 32-bit non-cached and 32-bit cached operation over a typical range of memory wait states is 115%. The initial application of this processor circuit is on Stanford University's Gravity Probe-B experiment.
A Spacecraft Computer for High-Performance Applications
A high-performance processor circuit called the SC-3 has been developed to meet the requirements of advanced experiment and attitude control applications. It is based on the 16 MHz Intel 80386/80387 chip set and implements a dual bus system configuration which allows high-speed, 32-bit wide memory and low-speed. 16-bit wide Input Output(I/O) circuits to be separated. This separation maintains compatibility with a wide range of current I/O circuit designs while exploiting the high-bandwidth memory access capabilities of the 80386. Performance is further enhanced by means of a cache on the 32-bit bus. Gibson, Whetstone, and Dhrystone instruction mixes have been used to evaluate performance under various operating modes. When the SC-3 is constrained to execute from 16-bit memory. the Gibson mix indicates a 32% performance improvement compared to previous 16-bit processors. An average of 1.1 million Whetstones per second are performed over the typical range of memory wait states. The average Dhrystone performance improvement between 32-bit non-cached and 32-bit cached operation over a typical range of memory wait states is 115%. The initial application of this processor circuit is on Stanford University's Gravity Probe-B experiment.
