Session

Technical Session VIII: Advanced Technologies I

Abstract

This paper presents a new concept of building a high performance, radiation hardened computer from Commercial-Off-The-Shelf (COTS). We discuss the underlying radiation mitigation technologies used, and demonstrate their (radiation-tolerance) capabilities by citing the radiation test results. Hardness against Single Event Upsets (SEU) for COTS microprocessors is achieved using Time-Triple Modular Redundancy (TTMR). Single Event Functional Interrupts (SEFI) of the microprocessors are being mitigated with an auxiliary Hardened Coreä (H-Core) chip. The other on-board chips used are a combination of space qualified, radiation hardened COTS parts. A flight unit of the computer based on the above mentioned technologies, Proton 100k, was adapted for the Air Force Research Laboratory's Space Vehicles Directorate RoadRunner satellite program.

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Aug 10th, 2:30 PM

Low Power High-Speed Radiation Tolerant Computer

This paper presents a new concept of building a high performance, radiation hardened computer from Commercial-Off-The-Shelf (COTS). We discuss the underlying radiation mitigation technologies used, and demonstrate their (radiation-tolerance) capabilities by citing the radiation test results. Hardness against Single Event Upsets (SEU) for COTS microprocessors is achieved using Time-Triple Modular Redundancy (TTMR). Single Event Functional Interrupts (SEFI) of the microprocessors are being mitigated with an auxiliary Hardened Coreä (H-Core) chip. The other on-board chips used are a combination of space qualified, radiation hardened COTS parts. A flight unit of the computer based on the above mentioned technologies, Proton 100k, was adapted for the Air Force Research Laboratory's Space Vehicles Directorate RoadRunner satellite program.