Session
Technical Session VIII: Advanced Technologies I
Abstract
The Space Dynamics Laboratory has developed a hardware-based JPEG 2000 image compression solution and packaged it in a demonstration board. The board implements both Tier1 and Tier2 JPEG 2000 encoding in two Xilinx Virtex II FPGAs. The FPGA design was built as a first step toward developing JPEG 2000 image compression hardware that could be used for remote sensing on the ground, in the air, or in Earth orbit. This board has been used to demonstrate the power and flexibility of the JPEG 2000 standard in hardware, compressing both 8- bit and 12-bit grayscale images based on decoded image quality as well as output bit rate control. Images have also been compressed in both lossless and lossy modes. The board produces a JPEG 2000 file that includes all header and packet information needed to decode the output file. This paper will present the electrical design of the board and data flow. An application board of reduced size that maintains the same level of compression functionality has been conceptually designed.
Presentation Slides
An FPGA-based JPEG 2000 Demonstration Board
The Space Dynamics Laboratory has developed a hardware-based JPEG 2000 image compression solution and packaged it in a demonstration board. The board implements both Tier1 and Tier2 JPEG 2000 encoding in two Xilinx Virtex II FPGAs. The FPGA design was built as a first step toward developing JPEG 2000 image compression hardware that could be used for remote sensing on the ground, in the air, or in Earth orbit. This board has been used to demonstrate the power and flexibility of the JPEG 2000 standard in hardware, compressing both 8- bit and 12-bit grayscale images based on decoded image quality as well as output bit rate control. Images have also been compressed in both lossless and lossy modes. The board produces a JPEG 2000 file that includes all header and packet information needed to decode the output file. This paper will present the electrical design of the board and data flow. An application board of reduced size that maintains the same level of compression functionality has been conceptually designed.
